1. Technical Field
The invention relates to ferroelectric random access memories and methods of forming the same, and more particularly, to ferroelectric random access memories having lower electrodes respectively self-aligned to node conductive layer patterns and methods of forming the same.
2. Discussion of the Related Art
Generally, a ferroelectric random access memory (FRAM) has a plurality of capacitors. Each capacitor typically has the same structure as that of a dynamic random access memory (DRAM). That is, the capacitor includes a lower electrode, a dielectric layer, and an upper electrode, which are sequentially stacked on a semiconductor substrate. The upper electrode and the dielectric layer are formed to cover the lower electrode. The dielectric layer is not a composite layer including a silicon oxide (SiO2) layer and a silicon nitride (Si3N4) layer, but a ferroelectric layer. The lower electrode may have various shapes to increase its data storage capacity.
However, the lower electrode may be more difficult to form on the semiconductor substrate by using semiconductor fabrication processes in which the design rule of the FRAM has gradually been reduced. This is because a photolithography process may have a limitation in defining the lower electrodes on a photoresist layer with the reduction of the design rule of the FRAM. Furthermore, as the limitation of the photolithography process may influence a subsequent etching process, all the semiconductor fabrication processes related to the lower electrode may become more difficult to perform on the semiconductor substrate. Considering that the reduction of the design rule of the FRAM is generally unavoidable due to market demands for semiconductor devices, it may be required that the lower electrodes be embodied on a semiconductor substrate by providing ways to overcome the limitation of the photolithography process.
U.S. Pat. No. 6,268,260 to Douglas L. Keil (the '260 patent) discloses methods of forming memory cell capacitor plates in memory cell capacitor structure. According to the '260 patent, the method includes forming a sacrificial layer. An opening is formed in the sacrificial layer. An electrode material layer is formed on the sacrificial layer to partially fill the opening. Then, a portion of the electrode material layer is removed so that the remaining electrode material layer is down to at least about a level of the top surface of the sacrificial layer to define a memory cell capacitor plate. The memory cell capacitor plate may function as a lower electrode of a capacitor. Then, the sacrificial layer is removed.
However, the methods include forming the openings by performing photolithography and etching processes. The opening may not be formed in the sacrificial layer due to limits in performing the photolithography and etching processes as the design rule of a semiconductor device is gradually reduced. Further, the methods may involve many semiconductor fabrication processes, including forming the sacrificial layer to define the memory cell capacitor plate. This factor may be one reason for the increase in fabricating cost for a semiconductor device.